By Arthur H.M. van Roermund, Michiel Steyaert, Johan Huijsing
This e-book comprises the contribution of 18 tutorials of the twelfth Workshop on Advances in Analog Circuit layout. it really is quantity 12 within the winning sequence of Analog Circuit layout, delivering beneficial info and perfect overviews of analog circuit layout, CAD, and RF platforms. The sequence should be obvious as a connection with these inquisitive about analog and mixed-signal layout. every one booklet discusses 3 particular issues on new and priceless layout principles within the sector of analog circuit layout. every one subject is mentioned through six specialists within the box and cutting-edge info is shared and overviewed. during this twelfth version the themes are Fractional-N Synthesizers, layout for Robustness, and Line and Bus Drivers. Analog Circuit layout is a necessary reference resource for analog layout engineers and researchers that desire to preserve abreast with the newest advancements within the box. the educational insurance additionally makes it compatible to be used in a sophisticated layout direction.
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Extra info for Analog Circuit Design: Fractional-N Synthesizers, Design for Robustness, Line and Bus Drivers
In the case of the ‘and’ gate, either input can cause the output to transition. As gleaned from the figure, it is straightforward to determine which input is causing the transition, and appropriately pass its edge location value to the output of the ‘and’ gate. Similar arguments can be made for more complicated registers that include set and reset functions, and other primitives such as ‘or’ and ‘xor’ gates. 2 Fast Computation by Combining VCO and Divider Modules To obtain fast computation, we propose a technique that allows us to set the simulation sample period, according to the reference frequency rather than the much higher VCO frequency.
18 shows the microphotograph of the fractional-N synthesizer which is embedded in the quad-band direct conversion GSM/GPRS RF transceiver . To prevent switching noise in the fractional-N synthesizer from interfering with the 24 LNAs, the two circuits are separated by the low-noise baseband analog circuitry. N- and P-type substrate contacts under the baseband supply and ground shunt synthesizer switching noise in the substrate. 2 dB . 6. Conclusions Fractional-N frequency synthesis technique alleviates several PLL design constraints which are present in integer-N synthesizer design.
V. W. Schafer, “Discrete Time Signal Processing”, Prentice Hall, NJ, 1999. A. Demir, E. L. Sangiovanni-Vincentelli, and I. Vassiliou, “Behavioral Simulation Techniques for Phase/Delay-Locked Systems”, Custom Integrated Circuits Conference (CICC), pages 453-456, 1994. H. Perrott, “Techniques for High Data Rate Modulation and Low 49 Power Operation of Fractional-N Frequency Synthesizers with Noise Shaping”, PhD Thesis, MIT, 1997. be Abstract Does fractional-N synthesis offer the way out for monolithic CMOS integration of high-quality transceivers?